【 Features 】 |
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Supports dual port USB-C; CC0_A/CC0_B and CC1_A/CC1_B |
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CC Logic and PD3.1 Engine supporting one Charging Upstream-facing Port (UFP) and one Dual Role Power (DRP) with Fast Role Swap (FRS) |
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-Built-in pull-up/pull-down resistors (Rp and Rd) |
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USB-C Charging UFP Capability |
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-Charging connected PD hosts once external power is available |
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-Supports Provider and Consumer roles |
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-Support PD Power Rule up to 140W |
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-Support dead battery charging and FRS |
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USB-C DRP Capability |
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-Supports Provider and Consumer roles |
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-Support PD Power Rule up to 140W as Sink and 140W as Source |
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DP Alt-mode Configuration |
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-Built-in Aux_CH switch |
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Supports USB Billboard Device |
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In-System-Programming (ISP) through USB-C |
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Supports DP 1.4 pass through |
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On-chip Full-Speed USB Slave which is compliant to USB 2.0 Specification |
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MCU Subsystem |
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-8051 core with 128K bytes Flash, 256 bytes Direct RAM and 4K bytes on-chip auxiliary RAM |
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-Fast CPU rate (24Mhz). 41.6 ns for shortest instruction |
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-Programmable CPU clocks from 24 Mhz to 500 Khz |
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-Programmable crystal start-up cycles from 0 to 4096 cycles |
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-Supports Idle mode and Stop mode for power saving |
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-Supports crystal/CPU wake-up from Stop mode |
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-Up to 26 GPIOs |
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-Supports external interrupts on 2 GPIO pins |
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-Supports keyboard interrupt on 4 GPIO pins |
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-4 Timers; On-chip 15-bit programmable Watchdog Timer |
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-Serial Port supports Synchronous mode and 8/9-bit UART modes |
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-DAC to sense the Analog Input Level |
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-Two I2C Master and two I2C Slave ports with configurable pin outs |
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-DAC and External Interrupt pins can be additional GPIO if the associated function is not enabled |
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-Low Voltage Inhibit (LVI) circuit which provides reliable power up reset and prevent accidental data loss in Flash |
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Single 3.3V CMOS design |
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40-pin QFN (5mm x 5mm) package |