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smartSD controllers

WT5270

WT5270 is a smartSD controller compatible to SD Physical Layer Specification Version 3.00 and below. WT5270 supports full coverage of card capacity on portable and stationary applications, including the Standard Capacity SD Memory Card (SDSC), the High Capacity SD Memory Card (SDHC) and the Extended Capacity SD Memory Card (SDXC, larger than 32 GB up to and including 2 TB). WT5270 provides support for most NAND Flash currently in the market, including Micron, Samsung, Toshiba and Hynix, etc.
WT5270 also supports In-System-Programming (ISP) to speed up developing new I/O applications and adapting for new memory models. For smartSD Card applications, firmware codes of the internal micro-controller are encrypted and stored in external memory such as NAND Flash, serial Flash or serial EEPROM.
WT5270 supports SD clock at 0 ~ 100 MHz with SD 1-bit/4-bit and SPI 1-bit data transfer modes. The I/O interface provides a variety of I/O functions, including UART, SPI Master Mode, SD Host and ISO7816. It also includes additional GPIO pins with configurable pull-up and pull-down resistors.

Features

- SD system interface and specification
-Support SD 1-bit/4-bit mode and SPI mode, Support SD clock 0 ~ 100 MHz

-Support UHS-1 50 mode type

-Compliant to SD Physical Layer Specification V3.00 (>32GB card capacity, SDXC), V2.00 (>2GB and ≤ 32GB card capacity, SDHC) and V1.10 (≤2GB card capacity, SDSC)

-2.7V to 3.6V operating voltage
- I/O interface
-SD/SDIO host:

Connect to 1~2 I/O chips with SD/SDIO interface 1-bit/4-bit mode

Configurable SD Host clock rate from 1/2 ~ 1/1024 system clock frequency (throughput up to 160M bits per second)

-Hardware crypto engine:

DES, TDES (EDE/EEE) and AES (128/192/256)

DMA

Support ECB, CBC, CFB and OFB modes

-Two SPI-masters:

Configurable operation mode: half-duplex/full-duplex

DMA

One SPI-master supports serial Flash 2/4-bit I/O mode

Configurable SPI clock frequencies up to 40MHz

Configurable CRC polynomial (0 ~ 32 bits) for optional data protection

Configurable inter-byte delays

-ISO7816 controller:

T=0 and T=1

DMA

Configurable max. retry count for byte parity error handling (T=0)

Auto LRC/CRC option (T=1)

-Two UART interfaces

-GPIO with configurable pull-up and pull-down resisters
- NAND Flash interface
-Support 3.3V 8-bit data bus and 1 ~ 8 NAND Flash chips

-Support 512/2K/4K/8K Bytes per page SLC/MLC NAND Flash memory with SDR interface mode

-Support BCH ECC 8/15/24/40/44/60 bits data protection for various NAND Flash memory

-Optimized Flash memory management to maximize the data endurance and performance

-Configurable Flash interface access timing
- System Operation
-Configurable internal oscillator (system clock) frequency (16MHz ~ 80MHz)

-Oscillator or crystal pad for an optional external clock source

-Load MCU code from an external memory chip (NAND Flash, SPI serial Flash, SPI serial EEPROM)

-Dynamic MCU code segment loading during controller operation. Extendable total MCU code size.

-In-System Program (ISP)

Weltrend March 2025 Revenue Report

WT5270